Intel cache Evolutions

Problem
1. External memory slower than the system bus.

• Solution : Add external cache using faster memory technology.

• Processor on which feature first appears : 386

2. Increased processor speed results in external bus becoming a bottleneck for cache access.

• Solution : Move external cache on-chip, operating at the same speed as the processor.

• Processor on which feature first appears : 486

3. Internal cache is rather small, due to limited space on chip.

• Solution : Add external L2 cache using faster technology than main memory.

• Processor on which feature first appears : 486

4. Contention occurs when both the Instruction Prefetcher and the Execution Unit simultaneously require access to the cache. In that case, the Prefetcher is stalled while the Execution Unit’s data access takes place.

• Solution : Create separate data and instruction caches.

• Processor on which feature first appears : Pentium

5. Increased processor speed results in external bus becoming a bottleneck for L2 cache access.

• Solution : - Create separate back-side bus that runs at higher speed than the main (front-side) external bus. The BSB is dedicated to the L2 cache.

• Processor on which feature first appears : Pentium Pro

-Move L2 cache on to the processor chip.

• Processor on which feature first appears : Pentium II

6. Some applications deal with massive databases and must have rapid access to large amounts
of data. The on-chip caches are too small.

• Solution : - Add external L3 cache.

• Processor on which feature first appears : Pentium III

- Move L3 cache on-chip.

• Processor on which feature first appears : Pentium 4